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characteristics subject to change without notice 2062 2.4 03/27/09 smh4802 summit microelectronics, inc. ?summit microelectronics, inc., 2003 ? 1717 fox drive san jose, ca 95131 phone 408-436-9890 fax 408-436-9897 www.summitmicro.com preliminary information see last page programmable -48v hot-swap controller with forced shut down features & applications simplified application drawing soft start power supply live insertion into a -48v backplane programmable control of a dc/dc converter i 2 c power on/off control highly programmable circuit breaker active in-rush current limiting over-current filter circuit breaker immunity to voltage steps and current spikes programmable forced shutdown timer internal shunt regulator allows a wide supply range 14-pin soic package applications -48v power distribution telecom line cards central office switching high availability servers hot board insertion the smh4802 is designed to control in-rush current during hot swapping of plug-in cards operating in a distributed power environment. the device drives an external power mosfet switch that connects the supply to the load and protects against over-current conditions that might disrupt the host supply. it also provides under- voltage and over-voltage monitoring of the host power supply. when the source and drain voltages of the external mosfets are within specification it will provide a power good logic output that can be used to enable a dc/dc converter. additional features of the device include: temperature sense or master enable input, a 5v reference output for expanding monitor functions, and duty-cycle or latched over-current protection modes. an internal shunt regulator allows a wide supply range. the smh4802 -48v hot-swap controller also features a simple software i 2 c power on/off interface for remote power control applications. programming of configuration, control and calibration val- ues by the user can be simplified with the smx3200 interface adapter and a windows based gui supplied by summit. introduction figure 1. the drawing illustrates the smh4802 in a typical line-card application. it should be noted this is just an example, and the specific component values are purposely not shown. pin numbers reflect soic package. v dd uv ov pg# 5vref 2062 sad ?48v ret ?48v b sda scl dc/dc smh4802 fs# drain sense 14 5 4 10 12 9 8 11 1 ?48v a i 2 c header r d en/ts 3 v+ v? out? out+ on/ off vss cbsense vgate 6 7 2 r s v ss
2 smh4802 2062 2.4 03/27/09 summit microelectronics, inc. preliminary information functional block diagram the smh4802 is an integrated power controller for hot swappable add-in cards. the device operates from a wide supply range and generates the signals necessary to drive an isolated output dc/dc converter. as a typical add-in board is inserted into the powered backplane, physical connections must first be made with the chassis to discharge any electrostatic voltage potentials. the board then contacts the long pins on the backplane that provide power and ground. as soon as power is applied, the device starts up, but does not immediately apply power to the output load. under-voltage and over-voltage circuits inside the controller verify the input voltage is within the user-specified range. once these requirements are met, the hot-swap controller enables vgate to turn on the external power mosfet. the vgate output is current limited to i vgate, allowing the slew rate to be easily modified using external passive general description components. during the controlled turn-on period the v ds of the mosfet is monitored by the drain sense input. when drain sense drops below 2.5v, and vgate is greater than v dd ? v gt , the pg# output can begin turning on the dc/dc converter. steady state operation is maintained as long as all conditions are normal. any of the following events may cause the device to disable the dc/dc controller by shutting down the power mosfet: an under-voltage or over-voltage condition on the host power supply; an over- current event detected on the cbsense input; a failure of the power mosfet sensed via the drain sense pin; the master enable (en/ts) falling below 2.5v; or the fs# input being driven low by events on the secondary side of the dc/dc controller. if one of these events occurs the smh4802 can be configured so vgate shuts off and either latches into an off state or recycles power after a cooling down period, t cyc . figure 2. functional block diagram. pin numbers reflect soic package. programmed delay programm- able delay + ? + ? + ? programmed quick-trip 50mv duty cycle timer + ? + ? 5v 2.5v 12v vgate sense + ? vdd vss cbsense en/ts scl sda uv ov pg# drain sense vgate 5.0vref 12vref 2062 bd programmable shutdown timer fs# 14 3 1 5 9 7 4 8 6 2 11 12 10 200k ? ? ?
3 2062 2.3 6/19/03 smh4802 summit microelectronics, inc. preliminary information pin configuration pin descriptions 2062 pin table a drain sense vgate en/ts sda scl cbsense v ss v dd nc pg# 5vref fs# ov uv 1 2 3 4 5 6 7 14 13 12 11 10 9 8 2062 14 pcon 14-pin soic note: pin numbers reflect the 14 pin soic package. drain sense vgate en/ts nc sda scl cbsense v ss v dd nc pg# nc 5vref fs# ov uv 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 2062 16 pcon 16-pin ssop (engineering only) . o n n i pe p y te m a n n i pn o i t p i r c s e d n i p 1 i n i a r d e s n e s e h t ( t e f s o m e h t f o n i a r d e h t t a e g a t l o v e h t s r o t i n o m t u p n i e s n e s n i a r d e h t v o t t c e p s e r h t i w s i e r u s a e m s s 0 1 l a n r e t n i n a . ) n i a r d e h t s l l u p e c r u o s a w o l e b d l e h e b t s u m e s n e s n i a r d . l e v e l f e r v 5 e h t s d r a w o t l a n g i s e s n e s . t u p t u o # g p e h t e l b a n e o t v 5 . 2 2 oe t a g v v o t l a u q e y l r a e n , t u p t u o e v i r d e d i s h g i h a s i t u p t u o e t a g v e h t d d n r u t o t d e s u , t u p t u o t n e r r u c t n a t s n o c a s e i l p p u s l a n g i s s i h t . t e f s o m r e w o p l a n r e t x e n a n o 0 0 1 ( . e t a r w e l s n o - n r u t t e f s o m e h t f o t n e m t s u j d a y s a e s w o l l a h c i h w ) l a c i p y t a 3 is t / n e e b l l i w e t a g v . t u p n i e l b a n e r e t s a m e h t s i t u p n i e s n e s e r u t a r e p m e t / e l b a n e e h t k 0 0 2 l a n r e t n i n a s a h n i p s i h t . v 5 . 2 n a h t s s e l s i s t / n e f i d e l b a s i d . v 5 o t p u l l u p 4 o / ia d s . t u p t u o n i a r d n e p o n a s a d e r u g i f n o c s i t i . n i p a t a d l a i r e s l a n o i t c e r i d i b e h t s i a d s k 0 5 l a n r e t n i n a s i e r e h t . f e r v 5 o t d e t c e n n o c r o t s i s e r 5 il c s n i . s r e t s i g e r n o i t a r u g i f n o c e h t f o t u o d n a o t n i a t a d k c o l c o t d e s u s i t u p n i l c s e h t d a e r e h t n i . h g i h s i l c s e l i h w a d s n o e l b a t s n i a m e r t s u m a t a d e d o m e t i r w e h t k 0 5 l a n r e t n i n a s i e r e h t . l c s f o e g d e g n i l l a f e h t n o t u o d e k c o l c s i a t a d e d o m . f e r v 5 o t d e t c e n n o c r o t s i s e r 6 ie s n e s b c s s o r c a s n o i t i d n o c t n e r r u c - r e v o t c e t e d o t d e s u s i t u p n i e s n e s r e k a e r b t i u c r i c e h t r ( r o t s i s e r e s n e s e u l a v w o l , l a n r e t x e n a s . t e f s o m r e w o p e h t h t i w s e i r e s n i d e i t ) t n a h t r e g n o l r o f r o t s i s e r e h t s s o r c a v m 0 5 n a h t r e t a e r g f o p o r d e g a t l o v a d b c l l i w v o t y l t c e r i d n i p e h t t c e n n o c e s n e s b c e l b a s i d o t . r e k a e r b t i u c r i c e h t p i r t s s a . . e l b a l i a v a o s l a s i t n i o p e s n e s p i r t - k c i u q e l b a m m a r g o r p 7 r w pv s s v s s f e r v 5 e h t d n a s t u p n i l l a . y l p p u s e h t f o e d i s e v i t a g e n , e h t o t d e t c e n n o c s i v o t d e c n e r e f e r e r a t u p t u o s s . 8 iv u n o i t c n u j n o c n i y l l a c i p y t , r o t i n o m y l p p u s e g a t l o v - r e d n u n a s a d e s u s i n i p v u e h t . v 5 . 2 n a h t s s e l s i v u f i d e l b a s i d e b l l i w e t a g v . r e d d a l r o t s i s e r l a n r e t x e n a h t i w n i e l b a t s u j d a , t u p n i v u e h t n o e l b a l i a v a s i s i s e r e t s y h l a n r e t n i e l b a m m a r g o r p a . t u p n i v u e h t n o e l b a l i a v a o s l a s i y a l e d r e t l i f a . v m 5 . 2 6 f o s t n e m e r c n i
4 smh4802 2062 2.3 6/19/03 summit microelectronics, inc. preliminary information pin descriptions ( continued ) 2062 pin table b note: pin numbers reflect the 14 pin soic package. . o n n i pe p y te m a n n i pn o i t p i r c s e d n i p 9 iv o n o i t c n u j n o c n i y l l a c i p y t , r o t i n o m y l p p u s e g a t l o v - r e d n u n a s a d e s u s i n i p v o e h t n a h t r e t a e r g s i v o f i d e l b a s i d e b l l i w e t a g v . r e d d a l r o t s i s e r l a n r e t x e n a h t i w . t u p n i v o e h t n o e l b a l i a v a o s l a s i y a l e d r e t l i f a . v 5 . 2 0 1 i# s f # g p e h t d n a e t a g v s e s u a c t a h t t u p n i w o l e v i t c a n a s i n i p n w o d t u h s d e c r o f e h t . d e r i p x e s a h r e m i t f f o - d l o h l a n r e t n i n a r e t f a e m i t y n a t a n w o d t u h s e b o t t u p t u o e r a h c i h w ( e d i s y r a d n o c e s e h t n o s t i u c r i c y r o s i v r e p u s s w o l l a r e m i t f f o - d l o h e h t - o t p o n a a i v 2 0 8 4 h m s e h t f o n w o d t u h s l o r t n o c o t ) y l l a i t i n i p u d e r e w o p t o n . r o t s i s e r p u l l u p o n s a h t u p n i s i h t . r o t a l o s i 1 1 of e r v 5 t u p n i c i g o l e h t d n a p x e o t d e s u e b y a m t a h t e g a t l o v e c n e r e f e r t u p t u o v 5 a s i s i h t v o t t c e p s e r h t i w s i t u p t u o e c n e r e f e r e h t . 2 0 8 4 h m s e h t n o s n o i t c n u f s s . 2 1 o# g p e b n a c t i . r o t s i s e r p u l l u p l a n r e t n i o n h t i w t u p t u o w o l - e v i t c a , n i a r d - n e p o n a s i # g p 3 r e t f a d e l b a n e s i # g p . r e t r e v n o c c d / c d a e l b a n e r o d a o i a h c t i w s o t d e s u v s e h c a e r e t a g v : s t n e v e d d v - t g , v 5 . 2 n a h t s s e l s i e g a t l o v e s n e s n i a r d e h t , d e e c x e t o n n a c n i p s i h t n o e g a t l o v . d e r i p x e s a h e m i t y a l e d d e m m a r g o r p e h t d n a v o t d e c n e r e f e r s a v 2 1 s s . 3 1 c nc nn o i t c e n n o c o n 4 1 r w pv d d v d d d e t c e n n o c r o t a l u g e r t n u h s l a n r e t n i n a . n o i t c e n n o c y l p p u s e v i t i s o p e h t s i v n e e w t e b d d v d n a s s . 2 0 8 4 h m s e h t s e i l p p u s t a h t v 2 1 y l e t a m i x o r p p a s p o l e v e d v e h t h t i w s e i r e s n i d e c a l p e b t s u m r o t s i s e r a d d t n e r r u c r o t a l u g e r e h t t i m i l o t n i p r ( d . ) s n o i t a r t s u l l i n o i t a c i l p p a e h t n i
5 2062 2.4 03/27/09 smh4802 summit microelectronics, inc. preliminary information temperature range ............ (industrial) ?40c to 85c .......................................... (commercial) ?5c to 70c t j(max) ................................................................ 150c r j-a .....................................................* 88c/w r j-c .......................................................* 37c/w note ? the device is not guaranteed to function outside its operating rating. stresses listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions outside those listed in the operational sections of this specification is not implied. exposure to any absolute maximum rating for extended periods may affect device performance and reliability. * 14 pin soic. temperature under bias ..................... ?55c to 125c storage temperature .......................... ?65c to 150c lead solder temperature (10 secs) .................. 300c terminal voltage with respect to v ss : v dd ............................................. ?0.5v to v dd ov, uv, drain sense, scl, sda, fs#, cbsense ........................ ?0.5v to v dd +0.5v en/ts ....................................................... 10v pg# .................................. ?0.5v to v dd +0.5v vgate ........................................... v dd +0.5v absolute maximum ratings* recommended operating conditions dc operating characteristics ( over recommended operating conditions; voltages are relative to v ss , except v gt ) 2062 elect table l o b m y sr e t e m a r a ps n o i t i d n o c. n i m. p y t. x a ms t i n u v d d e g a t l o v y l p p u si d d a m 3 =1 12 13 1v v 5 f e r t u p t u o e c n e r e f e r v 5i d d a m 3 =5 7 . 40 0 . 55 2 . 5v i 5 d a o l t n e r r u c t u p t u o e c n e r e f e r v 5i d d a m 3 =1 ?1a m i d d t n e r r u c y l p p u s r e w o p20 1a m v v u d l o h s e r h t e g a t l o v - r e d n ui d d a m 3 =5 7 4 . 20 0 5 . 25 2 5 . 2v v t s y h v u s i s e r e t s y h e g a t l o v - r e d n ui d d a m 3 =3 6v m v v o d l o h s e r h t e g a t l o v - r e v oi d d a m 3 =5 7 4 . 20 0 5 . 25 2 5 . 2v v t s y h v o s i s e r e t s y h e g a t l o v - r e v oi d d a m 3 =0 1v m v e t a g v e t a g e g a t l o v t u p t u o v d d v i e t a g v e t a g t u p t u o t n e r r u c0 0 1a v e s n e s d l o h s e r h t e s n e s n i a r di d d a m 3 =5 7 4 . 20 0 5 . 25 2 5 . 2v i e s n e s t u p t u o t n e r r u c e s n e s n i a r dv e s n e s v = s s 9 ?0 1 ?1 1 ?a v b c d l o h s e r h t r e k a e r b t i u c r i ci d d a m 3 =0 40 50 6v m v b c q t i u c r i c p i r t k c i u q e l b a m m a r g o r p d l o h s e r h t r e k a e r b 0 0 2v m 0 0 1v m 0 6v m f f o? v s t / n e d l o h s e r h t s t / n ei d d a m 3 =5 7 4 . 20 0 5 . 25 2 5 . 2v v t s y h s t / n e s i s e r e t s y h s t / n ei d d a m 3 =0 1v m v l o # g p e g a t l o v w o l t u p t u oi l o a m 3 =0 4 . 0v i l i s t / n e t n e r r u c t u p n iv l i v = s s 0 0 1a v t g v ( d l o h s e r h t e t a g t g v = d d v ? e t a g )7 . 08 . 10 . 3v
6 smh4802 2062 2.4 03/27/09 summit microelectronics, inc. preliminary information l o b m y sn o i t p i r c s e d. n i m. p y t. x a ms t i n u t d b c ) r e t l i f ( y a l e d r e k a e r b t i u c r i c v m 0 5 e l b a m m a r g o r p 5 s * 0 5 0 5 1 0 0 4 t d g p y a l e d d o o g r e w o p e l b a m m a r g o r p * 5 s m 0 2 0 8 0 6 1 t d s t q d n w o d t u h s p i r t k c i u q 0 0 2s n t c y c e m i t e l c y c r e k a e r b t i u c r i c 5 . 2s 5s t f v u p r e t l i f e g a t l o v - r e v o / - r e d n u e l b a m m a r g o r p * f f o 5s m 0 8s m 0 6 1s m t d s y a l e d p u t r a t s 5 . 0s m 5s m * 0 8s m 0 6 1s m coptgcctstcs * defaultvalue after uv and ov become valid there is a delay ? t sd ? that precedes the turn on of vgate. see figure 6. fast shut down delay from fault to the beginning of vgate off. 2062 ac table
7 2062 2.4 03/27/09 smh4802 summit microelectronics, inc. preliminary information i 2 c 2-wire serial interface ac operating characteristics figure 3 shows a timing diagram for the bus interface memory timing. one bit of data is transferred during each clock pulse. note that data must remain stable when the clock is high. i 2 c 2-wire serial interface ac operating characteristics t f t r t low t high t hd:sda t su:sda t buf t dh t hd:dat t su:dat t su:sto scl sda in sda out t aa 2050 fig09 2.0 figure 3. bus interface memory timing 2062 intf. table l o b m y sr e t e m a r a ps n o i t i d n o c. n i m. x a ms t i n u f l c s y c n e u q e r f k c o l c l c s 00 0 1z h k t w o l d o i r e p w o l k c o l c 7 . 4s t h g i h d o i r e p h g i h k c o l c 0 . 4s t f u b e m i t e e r f s u bn o i s s i m s n a r t w e n e r o f e b7 . 4s t a t s : u s e m i t p u t e s n o i t i d n o c t r a t s 7 . 4s t a t s : d h e m i t d l o h n o i t i d n o c t r a t s 0 . 4s t o t s : u s e m i t p u t e s n o i t i d n o c p o t s 7 . 4s t a a t u p t u o d i l a v o t e g d e k c o l c) n e l c y c ( a d s d i l a v o t w o l l c s2 . 05 . 3s t h d e m i t d l o h t u o a t a de g n a h c a d s o t ) 1 + n e l c y c ( w o l l c s2 . 0s t r e m i t e s i r a d s d n a l c s 0 0 0 1s n t f e m i t l l a f a d s d n a l c s 0 0 3s n t t a d : u s e m i t p u t e s n i a t a d 0 5 2s n t t a d : d h e m i t d l o h n i a t a d 0s n i ta d s d n a l c s r e t l i f e s i o nn o i s s e r p p u s e s i o n0 0 1s n t r w e m i t e l c y c e t i r w 5s m
8 smh4802 2062 2.4 03/27/09 summit microelectronics, inc. preliminary information applications information powering v dd the 12v shunt regulator between the v dd and vss pins allows the smh4802 to operate over a wide range of supply voltages. it is necessary to use a series dropping resistor (r d ) between the host power supply and the v dd pin in order to bias the shunt regulator and limit current into the device. system enable the en/ts input provides an active high comparator input that may be used as a master enable or temperature sense input. under-/over-voltage sensing the under-voltage (uv) and over-voltage (ov) inputs provide a set of comparators that act in conjunction with an external resistor divider network to sense when the host supply voltage exceeds the user defined limits. if the input to the uv pin rises above 2.5v, and the input to the ov pin falls below 2.5v, the power-up sequence may be initiated. if uv falls below 2.5v, or ov rises above 2.5v, the pg# and vgate outputs will be shut down immediately. under-/over-voltage filtering the smh4802 may also be configured so that an out of tolerance condition on uv/ov will not shut off the output immediately. a filter delay can be inserted so that only sustained under-voltage or over-voltage conditions will shut off the output. an out of tolerance condition on uv/ ov for longer than the filter delay time (t uofltr ) will latch the vgate and pg outputs in the off state if the uv/ov filter option is enabled. the under-/over-voltage filter- ing feature is disabled in the default configuration of the device. under-voltage hysteresis the under-voltage comparator input may be configured with a programmable level of hysteresis. the compare level may be set in steps (up to 15) of 62.5mv below 2.5v. the default under-voltage hysteresis level is set to 62.5mv. soft start slew rate control once all of the preconditions for powering up the dc/dc converters have been met, the smh4802 provides a means to soft start the external power fet limiting the in-rush current. current limiting is generally needed due to the bulk capacitance across the power rails of the dc/dc convert- ers. the vgate output of the smh4802 is current limited to i vgate , allowing the slew rate to be easily modified using external passive components. load control ? turning on a dc/dc converter once power has been ramped to the dc/dc converter, two conditions must be met before the pg# output can be asserted: the drain sense voltage must be below 2.5v, and the vgate voltage must be greater than v dd ? v gt . the drain sense input ensures the power mosfet is not absorbing too much steady state power from operat- ing at a high v ds . (this sensor remains active at all times, except during the current regulation period). the vgate sensor ensures the power mosfet is operating well into its saturation region before allowing the loads to be switched on. once vgate reaches v dd ? v gt this sensor is latched. after the external mosfet is properly switched on, the pg# output will be asserted after a delay of t pgd. the delay time is programmable from 5ms to 160ms. note: the pg# output has a 12v withstand capability, so high voltages must not be connected to this pin. a bipolar transistor or an opto-isolator can be used to boost the withstand voltage to that of the host supply. force shutdown ? secondary feedback the force shutdown signal (fs#) is an active low input that provides a method of receiving feedback from the secondary side of the dc/dc controllers. a built-in hold- off timer allows the smh4802 to ignore the state of the fs# input until the time period expires. the fs# input must be driven high by the end of this time period. if not, a low level on this input will shut off the vgate and pg# outputs. the purpose of the hold-off timer is to allow enough time for devices on the secondary side of the dc/dc controller to power-up and stabilize. this unique feature of the smh4802 allows supervisory circuits, such as an sms44, to control the shutdown of the primary side soft start circuit, even though the secondary side initially has no power. circuit breaker operation the smh4802 provides a number of circuit breaker functions to protect against over current conditions. a sustained over-current event could damage the host supply and/or the load circuitry. the board?s load current passes through a series resistor (r s ) connected between the mosfet source (which is tied to cbsense) and v ss . the breaker trips (figure 4) whenever the voltage drop across r s is greater than 50mv for more than t cbd (a programmable filter delay ranging from 10s to 500s).
9 2062 2.4 03/27/09 smh4802 summit microelectronics, inc. preliminary information figure 6. power on timing sequence figure 5. circuit breaker cycle mode figure 4. under-/over-voltage filter timing applications information ( continued ) power-on timing figure 6 illustrates some power on sequences, including the uv and ov differentials to their reference, and power good cascading. refer to the ac operating characteristics table for more information on the t cbd timing. note: in current regulation mode the drain sense signal will not affect the pg# output. 2062 fig06 v dd uv ov vgate drain sense 2.5v ref 2.5v ref 11 v dd 13 pg# 10 smh4802 2062 2.4 03/27/09 summit microelectronics, inc. preliminary information quick-trip tm circuit breaker (figure 7) the smh4802 provides a quick-trip feature that will cause the circuit breaker to trip immediately if the voltage drop across r s exceeds v qcb . the quick-trip can be disabled or set to 60mv, 100mv (default) or 200mv. current regulation the current regulation mode is an optional feature that provides a means to regulate current through the mosfet for a programmable period of time. it is generally enabled in applications that have switched dual (a and b) distrib- uted power sources. by using the current regulation function unwarranted shutdowns can be avoided if one of the dual supplies is switched in when it is at a more negative potential than the currently operating supply. when current regulation is selected it will be enabled during soft start (power on period) and during normal operation after the pg# output is enabled. if the voltage monitored at the cbsense pin is greater than 50mv, but less than v qcb , the smh4802 will reduce the vgate voltage in order to maintain a cbsense potential less than 60mv, effectively regulating the current through the mosfet. figures 8a and 8b illustrate the current regulation function. the time period t pcr ? selectable at 5, 80, or 320ms ? is the maximum time during which regulation will be enforced. if either v qcb or t pcr are exceeded the vgate and pg# outputs will immediately be de-asserted. however, if cbsense drops below 50mv before the timer ends, the timer is reset and vgate resumes normal operation. if the quick-trip level is exceeded then the device will bypass the current regulation timer and shut down imme- diately. the current regulation feature is disabled in the default configuration. operating at high voltages the breakdown voltage of the external active and passive components limits the maximum operating voltage of the smh4802 hot-swap controller. components that must be able to withstand the full supply voltage are: the input and output decoupling capacitors, the protection diode in series with the drain sense pin, the power mosfet switch and the capacitor connected between its drain and gate, the high-voltage transistors connected to the power good outputs, and the dropper resistor connected to the controller?s v dd pin. over-voltage and under-voltage resistors in figure 9 the three resistors (r1, r2, and r3) connected to the ov and uv inputs must be capable of withstanding the maximum supply voltage of several hundred volts. figure 7. circuit breaker quick trip response figure 8a. current regulation with recovery figure 8b. current regulation without recovery applications information ( continued ) 2062 fig08a v qcb vgate t crd 50mv 0v cbsense t pcr 12v 0v 2062 fig08b v qcb vgate 50mv 0v cbsense t pcr 12v 0v 2062 fig07 cbsense vgate 11 2062 2.4 03/27/09 smh4802 summit microelectronics, inc. preliminary information applications information ( continued ) notes: 1. the 10 ? () () ( ) ( ) ( ) ( ) ? ? ? ? ? ? ? ? ? ? ?
12 smh4802 2062 2.4 03/27/09 summit microelectronics, inc. preliminary information applications information ( continued ) of 250a for idmax is used to illustrate the following calculations. with v ov (2.5v) being the over-voltage trip point, r1 is calculated by the formula: ov max v r1 id = substituting: 2.5v r1 10k 250 a == next the minimum current that flows through the resistive divider, id min , is calculated from the ratio of minimum and maximum supply voltage levels : max min min max id vs id vs = substituting: min 250 a 36v id 125 a 2.5v == now the value of r3 is calculated from id min : min uv min vs v r3 id = v uv is the under-voltage trip point, also 2.5v. substitut- ing: 36v 2.5v r3 286k 125 a == the closest standard 1% resistor value is 267k then r2 is calculated: 2.5v r2 ? 10k 20k ? 10k 10k 125 a === or uv min v r2 ? r1 id = substituting: 2.5v r2 ? 10k 20k ? 10k 10k 125 a === an excel spread sheet is available on summit?s website ( www.summitmicro.com ) to simplify the resistor value calculations and tolerance analysis for r1, r2, and r3. dropper resistor selection the smh4802 is powered from the high-voltage supply via dropper resistor r d . the dropper resistor must provide the smh4802 (and its loads) with sufficient operating current under minimum supply voltage condi- tions, but must not allow the maximum supply current to be exceeded under maximum supply voltage conditions. the dropper resistor value is calculated from: max min dd d dd load vs ? v r i?i = where vs min is the lowest operating supply voltage, v ddmax is the upper limit of the smh4802 supply voltage, i dd is minimum current required for the smh4802 to operate, and i load is any additional load current from the 2.5v and 5v outputs and between v dd and v ss . calculate the minimum wattage required for rd from: () min 2 max dd ro d vs ? v p r where v ddmin is the lower limit of the smh4802 supply voltage, and vs max is the highest operating supply voltage. in circumstances where the input voltage may swing over a wide range ( e.g., from 20v to 100v) the maximum current may be exceeded. in these circumstances it may be necessary to add an 11v zener diode between v dd and v ss to handle the wide current range. the zener voltage should be below the nominal regulation voltage of the smh4802 so that it becomes the primary regulator. mosfet v ds (on) threshold the drain sense input on the smh4802 monitors the voltage at the drain of the external power mosfet switch with respect to v ss . when the mosfet?s v ds is below the user-defined threshold the mosfet switch is consid- ered to be on. the v ds (on) threshold is adjusted using the resistor r t in series with the drain sense protection diode. this protection, or blocking, diode prevents high voltage breakdown of the drain sense input when the mosfet switch is off. a low leakage mmbd1401 diode offers protection up to 100v. for high voltage applications (up to 500v) the central semiconductor cmr1f-10m diode should be used. the v ds (on) threshold is calcu- lated from: () ( ) ds sense sense t diode threshold von v ?i ?r?v =
13 2062 2.4 03/27/09 smh4802 summit microelectronics, inc. preliminary information applications information ( continued ) where v diode is the forward voltage drop of the protection diode. the v ds (on) threshold varies over temperature due to the temperature dependence of v diode and i sense . the calculation below gives the v ds (on) threshold under the worst case condition of 85c ambient. using a 68k resistor for r t gives: () ( ) ds threshold v on 2.5v ? 15 a 68k ? 0.5v 1v == the voltage drop across the mosfet switch and sense resistor, v dss , is calculated from: () dss d s on virr = where i d is the mosfet drain current, rs is the circuit breaker sense resistor and r on is the mosfet on resistance. the dropper resistor value should be chosen such that the minimum and maximum i dd and v dd specifications of the smh4802 are maintained across the host supply?s valid operating voltage range. first, subtract the minimum v dd of the smh4802 from the low end of the voltage, and divide by the minimum i dd value. using this value of resistance as r d find the operating current that would result from running at the high end of the supply voltage to verify that the resulting current is less than the maximum i dd current allowed. if some range of supply voltage is chosen that would cause the maximum i dd specification to be vio- lated, then an external zener diode with a breakdown voltage of 11v should be used across v dd . as an example of choosing the proper r d value, assume the host supply voltage ranges from 36 to 72v. the largest dropper resistor that can be used is: (36v-11v)/3ma = 8.3k . next, confirm that this value of r d also works at the high end: (72v-13v)/8.3k = 7.08ma, which is less than 8ma. the fs# input can also be used in conjunction with a secondary-side supervisory circuit providing a positive feedback loop during the power up sequence. as an example, assume the smh4802 is configured to turn on ?48v to three dc/dc converters and then sequentially turn on the converters with a 1.6ms delay. further, assume all of the enable inputs are true and pg# has just been sequenced on. if fs# option 4 (100 bin in register 5) has been selected, then fs# must be driven high within 1.6ms after pg# goes low, otherwise the pg# output is disabled. ideally, there would be a secondary-side supervisor similar to the sms44 that would have its reset time-out period programmed to be less than 1.6ms. after the last supply turns on, the reset# output of the sms44 would be released and fs# pulled high. however, if for any reason not all of the supplies turn on, reset# is not released and the smh4802 disables the pg# output. soft start slew rate control the ?48v turn on time is controlled by the smh4802 and by the values of r8, c1 and c3 in figure 9. the turn on time is approximately 10ms with the component values shown. increasing the capacitance reduces the output slew rate and increases the turn on time. the capacitors prevent the mosfet from turning on simultaneously with the application of ?48v. resistor r8 is specified to limit the current into and the rate of charge of c1. the ratio of c1 to c3 (20:1) limits the mosfet?s v gs to approximately 2v once the ?48v supply is connected and c1 is fully charged.
14 smh4802 2062 2.4 03/27/09 summit microelectronics, inc. preliminary information development hardware & software programming connection the smh4802 uses the industry standard i 2 c 2-wire serial data interface. this interface provides access to the configuration registers and the nonvolatile fault latch. device configuration utilizing the windows based smh4802 graphical user interface (gui) is highly recom- mended. the software is available from the summit website ( www.summitmicro.com ). using the gui in conjunction with this datasheet simplifies the process of device prototyping and the interaction of the various functional blocks. a programming dongle (smx3200) is available from summit to communicate with the smh4802. the dongle connects directly to the parallel port of a pc and the target application. it programs the device through a cable using the i 2 c bus protocol. the smx3200 system consists of a programming dongle, cable and windows gui software. the device is then configured on-screen via an intuitive graphical user interface employing drop-down menus. it can be ordered on the website or from a local representative. the latest revisions of all software and an application brief describ- ing the smx3200 is available from the website. when design prototyping is complete, the software can generate a hex data file that should then be transmitted to summit for approval. summit will then assign a unique customer id to the hex code and program production devices before the final electrical test operations. this will ensure proper device operation in the end application. the windows gui software will generate the data and send it in i 2 c serial bus format so that it can be directly downloaded to the smh4802 via the programming dongle and cable. an example of the connection interface is shown in figure 10. when design prototyping is complete the software can generate a hex data file that should be transmitted to summit for approval. summit will then assign a unique customer id to the hex code and program production devices before the final electrical test operations. this will ensure proper device operation in the end application. caution: if the device is powered from -48v during programming damage may occur when connecting the dongle to a system utilizing an earth-connected positive terminal. either dis- abling the -48v connection or using a laptop computer is the best way to avoid damage. figure 10. smx3200 programmer i 2 c serial bus connections. pin numbers reflect soic package. pin 9, 5v pin 7, 10v pin5, reserved pin3, gnd pin 1, gnd pin 10, reserved pin 8, reserved pin 6, reserved pin 4, sda pin 2, scl top view of straight 0.1"
15 2062 2.4 03/27/09 smh4802 summit microelectronics, inc. preliminary information programming information i 2 c bus interface the i 2 c bus is a two-way, two-line serial communication between different integrated circuits. the two lines are: a serial data line (sda) and a serial clock line (scl). the smh4802 supports a 100 khz clock rate. the sda line must be connected to a positive supply by a pull-up resistor located on the bus. the smh4802 contains a schmitt input on both the sda and scl signals. start and stop conditions both the sda and scl pins remain high when the bus is not busy. data transfers between devices may be initiated with a start condition only when scl and sda are high. a high-to-low transition of the sda while the scl pin is high is defined as a start condition. a low-to-high transition on sda while scl is high is defined as a stop condition. figure 11 shows a timing diagram of the start and stop conditions. figure 11. start and stop conditions master/slave protocol the master/slave protocol defines any device that sends data onto the bus as a transmitter, and any device that receives data as a receiver. the device controlling data transmission is called the master, and the controlled device is called the slave. in all cases the smh4802 is referred to as a slave device since it never initiates any data transfers. acknowledge data is always transferred in bytes. acknowledge (ack) is used to indicate a successful data transfer. the transmitting device releases the bus after transmitting eight bits. during the ninth clock cycle the receiver pulls the sda line low to acknowledge that it received the eight bits of data. this is shown by the ack in figure 12. when the last byte has been transferred to the master during a read of the smh4802 the master leaves sda high for a not acknowledge (nack) cycle. this causes the smh4802 part to stop sending data, and the master issues a stop on the clock pulse following the nack. figure 12. acknowledge timing read and write the first byte from a master is always made up of a 7-bit slave address and the read/write (r/w) bit. the r/w bit tells the slave whether the master is reading data from the bus or writing data to the bus (1 = read, 0 = write). the first four of the seven address bits are called the device type identifier (dti). the dti for the smh4802 is 1010 bin . the next three bits are address values for a2, a1, and a0 (if multiple devices are used). the smh4802 issues an acknowledge after recognizing a start condi- tion and its dti. figure 13 shows an example of a typical master address byte transmission. figure 13. typical master address byte transmis- sion during a read by the master device the smh4802 trans- mits eight bits of data, then releases the sda line, and monitors the line for an acknowledge signal. if an acknowledge is detected, and no stop condition is generated by the master, the smh4802 continues to transmit data. if an acknowledge is not detected (nack) the smh4802 terminates any subsequent data transmis- sion. the read transfer protocol on sda is shown in figure 14. during a master write the smh4802 receives eight bits of data, then generates an acknowledge signal. the device continues to generate the ack condition on sda until a stop condition is generated by the master. the write transfer protocol on sda is shown in figure 15. random access read random address read operations allow the master to access any memory location in a random fashion. this operation involves a two-step process. first, the master issues a write command which includes the start condi- tion and the slave address field (with the r/w bit set to write) followed by the address of the word it is to read. this procedure sets the internal address counter of the smh4802 to the desired address. 2062 fig11 scl sda in start condition stop condition scl sda trans sda rec 1 2 3 8 9 ack 2062 fig12 scl sda 1 2 3 89 4 5 6 7 1 0 1 r/w 0 x x x ack 2062 fig13
16 smh4802 2062 2.4 03/27/09 summit microelectronics, inc. preliminary information programming information ( continued ) figure 16. sequential bus cycles figure 14. read protocol figure 15. write protocol after the word address acknowledge is received by the master it immediately reissues a start condition followed by another slave address field with the r/w bit set to read. the smh4802 responds with an acknowledge and then transmits the 8 data bits stored at the addressed location. at this point, the master sets the sda line to nack and generates a stop condition. the smh4802 discontinues data transmission and reverts to its standby power mode. sequential reads sequential reads can be initiated as either a current address read or a random access read. the first word is transmitted as with the other byte read modes (current address byte read or random address byte read). however, the master now responds with an acknowl- edge, indicating that it requires additional data from the smh4802. the smh4802 continues to output data for each acknowl- edge received. the master sets the sda line to nack and generates a stop condition. during a sequential read operation the internal address counter is automatically incremented with each acknowledge signal. for read operations all address bits are incremented, allowing the entire array to be read using a single read command. after a count of the last memory address the address counter rolls over and the memory continues to output data. master sda slave s t a r t 1 0 r / w 1 0 a c k xx x r xx x xx x xx a c k xx xx n a c k s t o p 2062 fig14 master sda slave s t a r t 1 0 r / w 1 0 a c k xx x w xx x xx x xx xx xx a c k a c k s t o p 2062 fig15 s t a r t a c k a 2 a 1 a 0 r / w a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a c k s t o p typical write operation typical read operation master sda slave master sda slave 2062 fig16 device identifier bus address 1 0 1 0 s t a r t a c k a 2 a 1 a 0 r / w a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 a c k device identifier bus address 1 0 1 0 a c k a 2 a 1 a 0 r / w s t o p s t a r t d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1 0 1 0 n a c k
17 2062 2.4 03/27/09 smh4802 summit microelectronics, inc. preliminary information register access the smh4802 contains a 2-wire bus interface for register access as explained in the previous section. this bus is highly configurable while maintaining the industry stan- dard protocol. the smh4802 responds to one of two selectable device type addresses: 1010 bin , generally assigned to nv-memories, or 1011 bin , which is the default address for the smh4802. the device type address is assigned by programming bit 3 of register 8. register accesses are also programmable using bits 2 and 1 of register 8. accesses can be denied (no reads or writes), read only, or read/write (default state). the smh4802 has three address pins (a2, a1 and a0) associated with the 2-wire bus. the smh4802 can be configured to respond only to the proper serial data string of the device type address and specific bus addresses (register 8, bit 0 set); or to the device type address and any bus address (register 8, bit 0 cleared). programming information ( continued ) master/slave protocol the master/slave protocol defines any device that sends data onto the bus as a transmitter and any device that receives data as a receiver. the device controlling data transmission is called the master and the controlled device is called the slave. the smh4802 is always a slave device since it never initiates any data transfers. one data bit is transferred during each clock pulse. the data on the sda line must remain stable during clock high time, because a change on the data line while scl is high is interpreted as either a start or a stop condition. register bit maps the smh4802 has eight user programmable, nonvolatile configuration registers. although 8-bit data transfers are used for reading and writing the registers, only the 4 least significant bits of each register are utilized by the device. therefore, in each of the following registers, bits 7 through 4 are left blank. bits 3 through 0 are used as shown for each register. default configuration register settings - smh4802-169 r e t s i g e r x e h s t n e t n o c n o i t p i r c s e d 2 0 r9 . l e v e l e c n e r e f e r t n e r r u c - r e v o p i r t - k c i u q d n a y a l e d t n e r r u c - r e v o 3 0 r2 . e l b a n e e d o m b c . y a l e d g n i c n e u q e s d o o g r e w o p 4 0 rb . e m i t e l c y c r e k a e r b t i u c r i c , y a l e d r e t l i f e g a t l o v - r e d n u / - r e v o , e l b a n e # g p 5 0 rc . l o r t n o c n o i t c n u f # s f , e l b a n e h c t a l t l u a f e l i t a l o v - n o n 6 0 rc . l o r t n o c n o i t a l u g e r t n e r r u c e t a g v , s e l b a n e r e t l i f e g a t l o v - r e v o d n a - r e d n u 7 0 r9 . l o r t n o c s i s e r e t s y h e g a t l o v - r e d n u 8 0 r1 i 2 r e t s i g e r n o i t a r u g i f n o c , s s e r d d a e p y t e c i v e d g n i d u l c n i , l o r t n o c c . l o r t n o c e s n o p s e r s s e r d d a e v a l s d n a , s u t a t s e t i r w / d a e r 9 0 r9 . d e e p s e c n e u q e s d o o g r e w o p c 0 r0 . d e t c e t e d s i t l u a f n e h w e r a w d r a h y b t e s . h c t a l t l u a f e l i t a l o v - n o n 2062regtable
18 smh4802 2062 2.4 03/27/09 summit microelectronics, inc. preliminary information 14 pin soic package packages 0.150 - 0.157 0.013 - 0.020 (0.33 - 0.51) 0.004 - 0.01 (0.10 - 0.25) 0.337 - 0.344 (8.55 - 8.75) 0.228 - 0.244 (5.80 - 6.20) 0.053 - 0.069 (1.35 - 1.75) 0.016 - 0.050 (0.40 - 1.27) (1.27) 0.0075 - 0.01 (0.19 - 0.25) 0.01 - 0.02 (0.25 - 0.50) (3.80 - 4.00) 14 pin soic x45o 0.016 - 0.050 0.05 0o min to 8o max 1 ref. jedec ms-012 inches (millimeters)
19 smh4802 2062 2.4 03/27/09 summit microelectronics, inc. preliminary information notice this is a preliminary information data sheet that describes a summit product currently in pre-production with limited characterization. summit microelectronics, inc. reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. summit microelectronics, inc. assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. charts and schedules contained herein reflect representative operating parameters, and may vary depending upon a user?s specific application. while the information in this publication has been carefully checked, summit microelectronics, inc. shall not be liable for any damages arising as a result of any error or omission. summit microelectronics, inc. does not recommend the use of any of its products in life support or aviation applications where the failure or malfunction of the product can reasonably be expected to cause any failure of either system or to significantly affect their safety or effectiveness. products are not authorized for use in such applications unless summit microelectronics, inc. receives written assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and (c) potential liability of summit microelectronics, inc. is adequately protected under the circumstances. ? copyright 2003 summit microelectronics, inc. power management for communications? revision 2.4 - this document supersedes all previous versions. i 2 c is a trademark of philips corporation. ordering information part marking smh4802 s nnn package s=14 lead soic part number suffix (see page 17) summit part number specific requirements are contained in the suffix such as commercial or industrial temp range, hex code, hex code revision, etc. . summit smh4802s xx a yy ww a nnn summit part number status tracking (blank, ms, es, 01, 02, ...) (summit use) date code (yy ww) lot tracking code (summit use) product tracking code (summit use) part number suffix (contains customer specific ordering requirements)

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